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PVT Variations Aware Robust Transistor Sizing for Power-Delay Optimal CMOS Digital Circuit Design.
Prateek Gupta
Shirisha Gourishetty
Harshini Mandadapu
Zia Abbas
Published in:
ISCAS (2019)
Keyphrases
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circuit design
digital circuits
design automation
power consumption
high speed
power dissipation
neural network
computationally efficient
power losses
real time