A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM.
Garima ThakralSaraju P. MohantyDhruva GhaiDhiraj K. PradhanPublished in: VLSI Design (2010)
Keyphrases
- power consumption
- low power
- optimization algorithm
- power management
- power saving
- inductive logic programming
- power dissipation
- high speed
- low cost
- global optimization
- optimization process
- cmos technology
- stability analysis
- low voltage
- power reduction
- evolutionary algorithm
- first order logic
- optimization problems
- chip design
- power transmission
- power losses