Instruction-Based Self-Testing of Processor Cores.

Nektarios Kranitis Antonis M. Paschalis Dimitris Gizopoulos Yervant Zorian

Published in: VTS (2002)

Keyphrases

level parallelism
instruction set
multi core processors
processor core
memory hierarchy
high speed
floating point
multimedia
parallel processing
test cases
computer architecture
distributed memory
parallel architectures
cache misses
central processing unit
learning disabled students