On-Chip Power Noise Reduction Techniques in High Performance SoC-Based Integrated Circuits.
Mikhail PopovichEby G. FriedmanRadu M. SecareanuOlin L. HartinPublished in: SoCC (2005)
Keyphrases
- noise reduction
- integrated circuit
- low power
- signal processor
- power consumption
- printed circuit boards
- edge preserving
- ibm power processor
- signal to noise ratio
- noise level
- built in self test
- edge detection
- single chip
- power dissipation
- chip design
- low cost
- noisy environments
- high speed
- median filter
- metal oxide semiconductor
- speech enhancement
- noise detection
- signal processing
- noise filtering
- noise free
- edge enhancement
- noise removal
- wiener filter
- noise cancellation
- cmos technology
- impulsive noise
- hearing aids
- electron beam
- edge preservation
- denoising
- multiscale