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A scalable and embedded FPGA architecture for efficient computation of grey level co-occurrence matrices and Haralick textures features.
Loïc Siéler
Camel Tanougast
Ahmed Bouridane
Published in:
Microprocess. Microsystems (2010)
Keyphrases
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grey level
efficient computation
gray level
texture features
grey levels
region growing
texture descriptors
hardware implementation
computational efficiency
texture analysis
databases
feature set
feature extraction
gray scale
segmentation method
connected components
database