Loïc Siéler

Publication Activity (10 Years)

Years Active: 2010-2018
Publications (10 Years): 6

Top Topics

Physiological Signals

Fpga Implementation

Top Venues

Biomed. Signal Process. Control.

Publications

Bo Zhang, Loïc Siéler, Yann Morère, Benoît Bolmont, Guy Bourhis
A Modified Algorithm for QRS Complex Detection for FPGA Implementation. Circuits Syst. Signal Process. 37 (7) (2018)
Shahid Khan, Hazrat Ali, Jamal Nasir, Loïc Siéler, Camel Tanougast
A U-shaped Wide band frequency reconfigurable dielectric resonator antenna for 5G applications. ISNCC (2018)
Mahdi Madani, Ilyas Benkhaddra, Camel Tanougast, Salim Chitroub, Loïc Siéler
Digital Implementation of an Improved LTE Stream Cipher Snow-3G Based on Hyperchaotic PRNG. Secur. Commun. Networks 2017 (2017)
Bo Zhang, Loïc Siéler, Yann Morère, Benoît Bolmont, Guy Bourhis
Dedicated wavelet QRS complex detection for FPGA implementation. ATSIP (2017)
Mahdi Madani, Ilyas Benkhaddra, Camel Tanougast, Salim Chitroub, Loïc Siéler
FPGA implementation of an enhanced SNOW-3G stream cipher based on a hyperchaotic system. CoDIT (2017)
Bo Zhang, Yann Morère, Loïc Siéler, Cécile Langlet, Benoît Bolmont, Guy Bourhis
Reaction time and physiological signals for stress recognition. Biomed. Signal Process. Control. 38 (2017)
Alaa Aldin Al Hariri, Fabrice Monteiro, Loïc Siéler, Abbas Dandache
Configurable and high-throughput architectures for Quasi-cyclic low-density parity-check codes. ICECS (2014)
Lucas Cicero, Camel Tanougast, Harry Ramenah, Loïc Siéler, F. Lecerf
A Li-Ion cell testbench for fast characterization and modeling. CoDIT (2014)
Alaa Aldin Al Hariri, Fabrice Monteiro, Loïc Siéler, Abbas Dandache
A high throughput configurable parallel encoder architecture for Quasi-Cyclic Low-Density Parity-Check Codes. IOLTS (2013)
Lionel Damez, Loïc Siéler, Alexis Landrault, Jean-Pierre Dérutin
Embedding of a real time image stabilization algorithm on a parameterizable SoPC architecture a chip multi-processor approach. J. Real Time Image Process. 6 (1) (2011)
Loïc Siéler, Camel Tanougast, Ahmed Bouridane
A scalable and embedded FPGA architecture for efficient computation of grey level co-occurrence matrices and Haralick textures features. Microprocess. Microsystems 34 (1) (2010)