A high throughput configurable parallel encoder architecture for Quasi-Cyclic Low-Density Parity-Check Codes.
Alaa Aldin Al HaririFabrice MonteiroLoïc SiélerAbbas DandachePublished in: IOLTS (2013)
Keyphrases
- high throughput
- low density parity check
- distributed video coding
- ldpc codes
- low complexity
- vlsi architecture
- microarray
- error correction
- decoding algorithm
- channel coding
- turbo codes
- rate distortion
- source coding
- message passing
- data acquisition
- unequal error protection
- rate allocation
- physical layer
- video codec
- error resilience
- bit rate
- motion estimation
- low power
- video coding
- bit error rate
- wyner ziv
- video compression
- low cost