On load latency in low-power caches.
Soontae KimNarayanan VijaykrishnanMary Jane IrwinLizy Kurian JohnPublished in: ISLPED (2003)
Keyphrases
- low power
- power consumption
- power reduction
- low cost
- high speed
- single chip
- digital signal processing
- wireless transmission
- high power
- cmos technology
- load balancing
- low power consumption
- logic circuits
- vlsi circuits
- gate array
- response time
- vlsi architecture
- low voltage
- power dissipation
- prefetching
- resource utilization
- image sensor
- error correction
- ultra low power
- energy efficiency