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Minimizing gate capacitances with transistor sizing.

Artur WróblewskiOtto SchumacherChristian V. SchimpfleJosef A. Nossek
Published in: ISCAS (4) (2001)
Keyphrases
  • silicon dioxide
  • high speed
  • low power
  • leakage current
  • integrated circuit
  • field effect transistors
  • cmos technology
  • real time
  • metal oxide semiconductor
  • power losses
  • databases
  • steady state
  • multiple input