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Layout design on multi-finger MOSFET for on-chip ESD protection circuits in a 0.18-μm salicided CMOS process.
Ming-Dou Ker
Che-Hao Chuang
Wen-Yu Lo
Published in:
ICECS (2001)
Keyphrases
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layout design
analog vlsi
high speed
chip design
circuit design
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integer programming
cmos technology
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random access memory
power dissipation
physical design
high density
linear programming