A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques.
Takuji MikiTakashi MorieKazuo MatsukawaYoji BandoTakeshi OkumotoKoji ObataShiro SakiyamaShiro DoshoPublished in: IEEE J. Solid State Circuits (2015)
Keyphrases
- analog to digital converter
- power consumption
- signal to noise ratio
- power supply
- low power
- received signal
- hd video
- synthetic aperture radar
- image enhancement
- noise reduction
- image sensor
- sar images
- random access memory
- image reconstruction
- image processing
- speckle noise
- cmos image sensor
- intelligent control
- single chip
- digital camera
- real time
- edge detection