Desgin for Testability of Asynchronous Sequential Circuits.
Jayashree SaxenaDhiraj K. PradhanPublished in: ICCD (1993)
Keyphrases
- delay insensitive
- asynchronous circuits
- high level synthesis
- shift register
- high speed
- analog circuits
- test data generation
- digital circuits
- real time
- sequential search
- machine learning
- data sets
- constraint satisfaction problems
- image processing
- search engine
- asynchronous communication
- state machines
- analog vlsi
- neural network