Full-Lock: Hard Distributions of SAT instances for Obfuscating Circuits using Fully Configurable Logic and Routing Blocks.
Hadi Mardani KamaliKimia Zamiri AzarHouman HomayounAvesta SasanPublished in: DAC (2019)
Keyphrases
- sat instances
- computational properties
- logic synthesis
- random instances
- delay insensitive
- sat solvers
- satisfiability problem
- asynchronous circuits
- digital circuits
- logic circuits
- sat problem
- random sat
- randomly generated
- phase transition
- stochastic local search
- probability distribution
- multi valued
- propositional satisfiability
- expressive power
- logic programs
- description logics
- floating gate
- boolean satisfiability
- random sat instances
- np complete
- search algorithm
- automated reasoning
- temporal logic
- built in self test