Nanoscale CMOS circuit leakage power reduction by double-gate device.
Keunwoo KimKoushik K. DasRajiv V. JoshiChing-Te ChuangPublished in: ISLPED (2004)
Keyphrases
- power reduction
- cmos technology
- low power
- power consumption
- power dissipation
- nm technology
- metal oxide semiconductor
- clock gating
- ultra low power
- low cost
- silicon on insulator
- high speed
- power saving
- low voltage
- equivalent circuit
- leakage current
- field effect transistors
- image sensor
- energy efficiency
- digital signal processing
- energy saving
- data center
- delay insensitive
- integrated circuit