Shared At-Speed BIST for Parallel Test of SRAMs with Different Address Sizes.

Tomonori Sasaki Yoshiyuki Nakamura Toshiharu Asaka

Published in: ATS (2008)

Keyphrases

built in self test
real world
real time
evolutionary algorithm
distributed shared memory
small size
massively parallel
statistical tests
parallel processing
test cases
control system
artificial neural networks
data structure
learning algorithm
genetic algorithm
databases
data sets