Sign in
Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability.
Steven M. Nowick
Niraj K. Jha
Fu-Chiung Cheng
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (1997)
Keyphrases
</>
asynchronous circuits
computationally efficient
delay insensitive
data sets
fault diagnosis
fault detection
process algebra
neural network
software engineering
shortest path