Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization.
Mingjie LiuWalker J. TurnerGeorge F. KokaiBrucek KhailanyDavid Z. PanHaoxing RenPublished in: DATE (2021)
Keyphrases
- neural network
- analog circuits
- fault diagnosis
- pattern recognition
- power losses
- optimization algorithm
- highly non linear
- digital circuits
- random walk
- fuzzy logic
- artificial neural networks
- bayesian networks
- neural network model
- weighted graph
- artificial intelligence
- genetic algorithm
- machine learning
- directed graph
- efficient optimization