Fault model for on-chip communication and joint equalization and special spacing rules for on-chip bus design.
Lei LiJianhao HuPublished in: Microelectron. Reliab. (2012)
Keyphrases
- high speed
- physical design
- circuit design
- single chip
- chip design
- programmable logic
- functional verification
- modular design
- vlsi implementation
- fault model
- evolvable hardware
- low cost
- ibm power processor
- high density
- cmos technology
- low power
- design methodology
- fault tolerant
- communication protocol
- information sharing
- analog vlsi
- design tools