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An interference miss isolation mechanism based on skewed mapping for shared cache in Chip Multiprocessors.
Anwen Huang
Chao Song
Wei Guo
Peng Li
Minxuan Zhang
Published in:
ASICON (2013)
Keyphrases
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multithreading
shared memory multiprocessors
multipath
distributed memory
high speed
prefetching
parallel computing
computational power
processor core
dynamic random access memory
data structure
high density
parallel implementation
class distribution
hit rate
memory subsystem
data distribution