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Majority Logic Circuit Minimization Using Node Addition and Removal.
Chang-Cheng Ko
Chia-Chun Lin
Yung-Chih Chen
Chun-Yao Wang
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2022)
Keyphrases
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peer to peer
digital circuits
logic synthesis
objective function
delay insensitive
high speed
logic circuits
automated reasoning
chip design
real time
asynchronous circuits