A parallel hardware architecture for connected component labeling based on fast label merging.
Holger FlattSteffen BlumeSebastian HesselbarthTorsten SchünemannPeter PirschPublished in: ASAP (2008)
Keyphrases
- connected component labeling
- hardware architecture
- binary images
- connected components
- processing elements
- hardware implementation
- quadtree
- hardware architectures
- morphological operations
- raster scan
- gray scale
- field programmable gate array
- associative memory
- parallel processing
- real time
- parallel architecture
- parallel implementation
- mathematical morphology
- multiresolution
- object recognition
- image processing