Login / Signup
A 45nm dual-port SRAM with write and read capability enhancement at low voltage.
D. P. Wang
Hung-Jen Liao
Hiroyuki Yamauchi
Y. H. Chen
Y. L. Lin
S. H. Lin
D. C. Liu
H. C. Chang
W. Hwang
Published in:
SoCC (2007)
Keyphrases
</>
low voltage
leakage current
cmos technology
random access memory
low power
power line
power consumption
read write
write operations
design considerations
image enhancement
electrical properties
image processing
power management
parallel processing
embedded dram
energy efficiency
edge detection