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An efficient implementation of FPGA based high speed IPSec (AH/ESP) core.
Muzaffar Rao
Thomas Newe
Edin Omerdic
Gerard Dooly
Elfed Lewis
Daniel Toal
Published in:
Int. J. Internet Protoc. Technol. (2018)
Keyphrases
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high speed
hardware implementation
frame rate
low power
hardware architecture
neural network
application specific
implementation details
real time
decision trees
general purpose
efficient implementation
network security