An Optimized BIST Architecture for FPGA Look-Up Table Testing.
Mahnaz Sadoughi YarandiArmin AlaghiZainalabedin NavabiPublished in: ISVLSI (2006)
Keyphrases
- hardware implementation
- hardware architecture
- hardware design
- software implementation
- real time
- fpga implementation
- dedicated hardware
- field programmable gate array
- fpga technology
- hardware architectures
- pipelined architecture
- high speed
- parallel architecture
- management system
- systolic array
- xilinx virtex
- efficient implementation
- software architecture
- test cases
- signal processing
- event driven
- data flow
- embedded systems
- reconfigurable hardware
- test data
- low cost