A modular architecture for a 6.4-Gbyte/s, 8-Mb DRAM-integrated media chip.
Takao WatanabeRyo FujitaKazumasa YanagisawaHitoshi TanakaKazushige AyukawaMitsuru SogaYuji TanakaYoshimitsu SugieYoshinobu NakagomePublished in: IEEE J. Solid State Circuits (1997)
Keyphrases