Kazushige Ayukawa

Publication Activity (10 Years)

Years Active: 1997-2001
Publications (10 Years): 0

Publications

Seiji Miura, Kazushige Ayukawa, Takao Watanabe
A dynamic-SDRAM-mode-control scheme for low-power systems with a 32-bit RISC CPU. ISLPED (2001)
Kazushige Ayukawa, Takao Watanabe, Susumu Narita
An access-sequence control scheme to enhance random-access performance of embedded DRAM's. IEEE J. Solid State Circuits 33 (5) (1998)
Takao Watanabe, Ryo Fujita, Kazumasa Yanagisawa, Hitoshi Tanaka, Kazushige Ayukawa, Mitsuru Soga, Yuji Tanaka, Yoshimitsu Sugie, Yoshinobu Nakagome
A modular architecture for a 6.4-Gbyte/s, 8-Mb DRAM-integrated media chip. IEEE J. Solid State Circuits 32 (5) (1997)