CMOS Pass-gate No-race Charge-recycling Logic (CPNCL).
Seung-Moon YooSung-Mo KangPublished in: ISCAS (1) (1999)
Keyphrases
- delay insensitive
- cmos technology
- random access memory
- logic programming
- power consumption
- low power
- charge coupled devices
- asynchronous circuits
- predicate logic
- classical logic
- multi valued
- chip design
- nm technology
- modal logic
- high speed
- low voltage
- gate dielectrics
- metal oxide semiconductor
- neural network
- low cost
- database
- focal plane
- digital circuits
- automated reasoning
- probability theory
- flip flops
- cd rom
- parallel processing