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Parallelized Network-on-Chip-Reused Test Access Mechanism for Multiple Identical Cores.
Taewoo Han
Inhyuk Choi
Hyunggoy Oh
Sungho Kang
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2016)
Keyphrases
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network on chip
routing algorithm
signal processing
fault tolerant