Asymmetric DRAM synthesis for heterogeneous chip multiprocessors in 3D-stacked architecture.
Minje JunMyoung-Jin KimEui-Young ChungPublished in: ICCAD (2012)
Keyphrases
- high density
- multithreading
- memory subsystem
- embedded dram
- vlsi implementation
- loosely coupled
- low cost
- cmos technology
- dynamic random access memory
- main memory
- random access memory
- management system
- design considerations
- level parallelism
- analog vlsi
- functional decomposition
- host computer
- cmos image sensor
- single chip
- parallel architecture
- real time
- software architecture
- sigma delta
- high speed