Minje Jun

Publication Activity (10 Years)

Years Active: 2007-2014
Publications (10 Years): 0

Top Topics

Random Access Memory

Top Venues

IEEE Trans. Computers

Publications

Seung-Hun Kim, Sang Hyong Lee, Minje Jun, Byunghoon Lee, Won Woo Ro, Eui-Young Chung, Jean-Luc Gaudiot
$C\!\!-\!\!Lock$ : Energy Efficient Synchronization for Embedded Multicore Systems. IEEE Trans. Computers 63 (8) (2014)
Minje Jun, Won Woo Ro, Eui-Young Chung
Exploiting Implementation Diversity and Partial Connection of Routers in Application-Specific Network-on-Chip Topology Synthesis. IEEE Trans. Computers 63 (6) (2014)
Minje Jun, Myoung-Jin Kim, Eui-Young Chung
Asymmetric DRAM synthesis for heterogeneous chip multiprocessors in 3D-stacked architecture. ICCAD (2012)
Minje Jun, Deumji Woo, Eui-Young Chung
Partial Connection-Aware Topology Synthesis for On-Chip Cascaded Crossbar Network. IEEE Trans. Computers 61 (1) (2012)
Minje Jun, Sungroh Yoon, Eui-Young Chung
Exploiting multiple switch libraries in topology synthesis of on-chip interconnection network. DATE (2010)
Minje Jun, Eui-Young Chung
Design of On-Chip Crossbar Network Topology Using Chained Edge Partitioning. Comput. J. 53 (7) (2010)
Jong-Ho Roh, Minje Jun, Kwanhu Bang, Eui-Young Chung
Jitter-Conscious Bus Arbitration Scheme for Real-Time Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2009)
Minje Jun, Sungjoo Yoo, Eui-Young Chung
Topology Synthesis of Cascaded Crossbar Switches. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (6) (2009)
Minje Jun, Sungjoo Yoo, Eui-Young Chung
Mixed integer linear programming-based optimal topology synthesis of cascaded crossbar switches. ASP-DAC (2008)
Minje Jun, Kwanhu Bang, Hyuk-Jun Lee, Eui-Young Chung
Latency-Aware Bus Arbitration for Real-Time Embedded Systems. IEICE Trans. Inf. Syst. (3) (2007)
Minje Jun, Kwanhu Bang, Hyuk-Jun Lee, Naehyuck Chang, Eui-Young Chung
Slack-based Bus Arbitration Scheme for Soft Real-time Constrained Embedded Systems. ASP-DAC (2007)