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Sequential circuit fault simulation using logic emulation.
Shih-Arn Hwang
Jin-Hua Hong
Cheng-Wen Wu
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (1998)
Keyphrases
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digital circuits
fault diagnosis
chip design
simulation model
delay insensitive
logic synthesis
fault detection
logic circuits
real time
neural network
modal logic
micron cmos
simulation models
asynchronous circuits