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A new verilog-A compact model of random telegraph noise in oxide-based RRAM for advanced circuit design.
Francesco Maria Puglisi
Nicolo Zagni
Luca Larcher
Paolo Pavan
Published in:
ESSDERC (2017)
Keyphrases
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probabilistic model
computational model
formal model
prior knowledge
conceptual model
neural network
similarity measure
multiscale
cost function
management system
theoretical analysis
mathematical model
circuit design
data sets
artificial neural networks
design automation