High-Speed Digital Double Sampling with Analog CDS on Column Parallel ADC Architecture for Low-Noise Active Pixel Sensor.
Yoshikazu NittaYoshinori MuramatsuKiyotaka AmanoTakayuki ToyamaJun YamamotoKoji MishinaAtsushi SuzukiTadayuki TauraAkihiko KatoMasaru KikuchiYukihiro YasuiHideo NomuraNoriyuki FukushimaPublished in: ISSCC (2006)
Keyphrases
- analog to digital converter
- high speed
- low power
- wide dynamic range
- mixed signal
- delta sigma
- image sensor
- dynamic range
- charge coupled device
- cmos image sensor
- vlsi architecture
- focal plane
- single chip
- power consumption
- high noise
- low cost
- low signal to noise ratio
- real time
- parallel processing
- digital circuits
- sampled data
- cmos technology
- sensor noise
- noise level
- signal to noise ratio
- data acquisition
- gaussian noise
- shared memory
- multi channel