Zhangxiaowen Gong

Publication Activity (10 Years)

Years Active: 2017-2022
Publications (10 Years): 7

Top Topics

Hardware Designs

Computer Systems

General Purpose

Single Instruction Multiple Data

Top Venues

Proc. ACM Program. Lang.

Publications

Zhangxiaowen Gong, Houxiang Ji, Yao Yao, Christopher W. Fletcher, Christopher J. Hughes, Josep Torrellas
Graphite: optimizing graph neural networks on CPUs through cooperative software-hardware techniques. ISCA (2022)
Zhangxiaowen Gong, Houxiang Ji, Christopher W. Fletcher, Christopher J. Hughes, Josep Torrellas
SparseTrain: Leveraging Dynamic Sparsity in Software for Training DNNs on General-Purpose SIMD Processors. PACT (2020)
Zhangxiaowen Gong, Houxiang Ji, Christopher W. Fletcher, Christopher J. Hughes, Sara Baghsorkhi, Josep Torrellas
SAVE: Sparsity-Aware Vector Engine for Accelerating DNN Training and Inference on CPUs. MICRO (2020)
Zhangxiaowen Gong, Houxiang Ji, Christopher W. Fletcher, Christopher J. Hughes, Josep Torrellas
SparseTrain: Leveraging Dynamic Sparsity in Training DNNs on General-Purpose SIMD Processors. CoRR (2019)
Zhangxiaowen Gong, Zhi Chen, Justin Josef Szaday, David C. Wong, Zehra Sura, Neftali Watkinson, Saeed Maleki, David A. Padua, Alexander V. Veidenbaum, Alexandru Nicolau, Josep Torrellas
An empirical study of the effect of source-level loop transformations on compiler stability. Proc. ACM Program. Lang. 2 (OOPSLA) (2018)
Neftali Watkinson, Aniket Shivam, Zhi Chen, Alexander V. Veidenbaum, Alexandru Nicolau, Zhangxiaowen Gong
Using Hardware Counters to Predict Vectorization. LCPC (2017)
Zhi Chen, Zhangxiaowen Gong, Justin Josef Szaday, David C. Wong, David A. Padua, Alexandru Nicolau, Alexander V. Veidenbaum, Neftali Watkinson, Zehra Sura, Saeed Maleki, Josep Torrellas, Gerald DeJong
LORE: A loop repository for the evaluation of compilers. IISWC (2017)