Volnei A. Pedroni

Publication Activity (10 Years)

Years Active: 1993-2018
Publications (10 Years): 2

Top Topics

Classifier Combination

Intrusion Detection

Finite State Machines

Network Security

Top Venues

IEEE Trans. Computers

Publications

Eduardo Viegas, Altair Olivo Santin, Luiz Oliveira, André França, Ricardo P. Jasinski, Volnei A. Pedroni
A reliable and energy-efficient classifier combination scheme for intrusion detection in embedded systems. Comput. Secur. 78 (2018)
Eduardo Viegas, Altair Olivo Santin, André França, Ricardo P. Jasinski, Volnei A. Pedroni, Luiz S. Oliveira
Towards an Energy-Efficient Anomaly-Based Intrusion Detection Engine for Embedded Systems. IEEE Trans. Computers 66 (1) (2017)
Volnei A. Pedroni
Introducing deglitched-feedback plus convergent encoding for straight hardware implementation of asynchronous finite state machines. ISCAS (2015)
Volnei A. Pedroni
XOR-decomposition principle and its use to build a glitch-free maximum-speed arbitrary binary waveform generator and deglitcher. ISCAS (2015)
André Luiz Pereira de França, Ricardo P. Jasinski, Paulo Cemin, Volnei A. Pedroni, Altair Olivo Santin
The energy cost of network security: A hardware vs. software comparison. ISCAS (2015)
Volnei A. Pedroni
Detailed analysis of implementation options for timed finite state machines in hardware. MWSCAS (2014)
Eduardo Peters, Ricardo P. Jasinski, Volnei A. Pedroni, Jean M. Simao
A new hardware coprocessor for accelerating Notification-Oriented applications. FPT (2012)
Volnei A. Pedroni, Ricardo P. Jasinski, Ricardo U. Pedroni
A very efficient single-iteration oldest-out data sorter. ISCAS (2011)
Ricardo P. Jasinski, Volnei A. Pedroni, Antonio Gortan, Walter Godoy Jr.
An Improved GF(2) Matrix Inverter with Linear Time Complexity. ReConFig (2010)
Antonio Gortan, Ricardo P. Jasinski, Walter Godoy Jr., Volnei A. Pedroni
Achieving near-MLD performance with soft information-set decoders implemented in FPGAs. APCCAS (2010)
Volnei A. Pedroni, Ricardo P. Jasinski, Ricardo U. Pedroni
Panning sorter: A minimal-size architecture for hardware implementation of 2D Data Sorting Coprocessors. APCCAS (2010)
Rui A. L. de Cristo, Ricardo P. Jasinski, Volnei A. Pedroni
Analysis and Preliminary Measurements of Radiated Emissions in an Asynchronous Circuit versus its Synchronous Counterpart. ReConFig (2010)
Volnei A. Pedroni, Ricardo U. Pedroni
PLL-less clock multiplier with self-adjusting phase symmetry. ISCAS (2006)
Volnei A. Pedroni
Phase sampling: a new approach to the design of LF direct digital frequency synthesizers. ISCAS (2006)
Volnei A. Pedroni, Bruno U. Pedroni
Output stage based high-resolution min/max and rank-order filters. IEEE Trans. Circuits Syst. II Express Briefs (1) (2005)
Volnei A. Pedroni
Compact Hamming-Comparator-based rank order filter for digital VLSI and FPGA implementations. ISCAS (2) (2004)
Fabio Sousa, Volker Mauer, Neimar Duarte, Ricardo P. Jasinski, Volnei A. Pedroni
Taking advantage of LVDS input buffers to implement sigma-delta A/D converters in FPGAs. ISCAS (1) (2004)
Volnei A. Pedroni
High-Resolution WTA-MAX Circuit for Large Networks. VLSI (2003)
Volnei A. Pedroni
Teaching Design-Oriented VHDL. MSE (2003)
Gert Cauwenberghs, Volnei A. Pedroni
A low-power CMOS analog vector quantizer. IEEE J. Solid State Circuits 32 (8) (1997)
Gert Cauwenberghs, Volnei A. Pedroni
A Charge-Based Parallel Analog Vector Quantizer. NIPS (1994)
Volnei A. Pedroni, Amnon Yariv
Learning in the hypercube. ICNN (1993)