Vinay Bhaskar Chandratre

Publication Activity (10 Years)

Years Active: 2008-2011
Publications (10 Years): 0

Publications

Menka Sukhwani, Vinay Bhaskar Chandratre, Megha Thomas, C. K. Pithawa, Vangmayee Sharda
500 MHz Delay Locked Loop Based 128-bin, 256 ns Deep Analog Memory ASIC "Anusmriti". ISVLSI (2011)
Shiv Kumar, Vinay Bhaskar Chandratre, Sudheer K. Mohammed, C. K. Pithawa
Extraction of Aspect Ratio for Non-Manhattan CMOS Devices. VLSI Design (2011)
Balaji Srinivasan, Vinay Bhaskar Chandratre
An Improved High Resolution CMOS Timing Generator Using Array of Digital Delay Lock Loops. VLSI Design (2010)
Balaji Srinivasan, Vinay Bhaskar Chandratre, Menka Tewani
0.35µ, 1 GHz, CMOS Timing Generator Using Array of Digital Delay Lock Loops. VLSI Design (2008)