0.35µ, 1 GHz, CMOS Timing Generator Using Array of Digital Delay Lock Loops.

Balaji Srinivasan Vinay Bhaskar Chandratre Menka Tewani

Published in: VLSI Design (2008)

Keyphrases

high speed
focal plane
circuit design
analog to digital converter
charge coupled device
image sensor
power consumption
low cost
low power
mixed signal
random access memory
infrared
concurrency control
power dissipation
neural network
dynamic range
analog vlsi
cmos image sensor