500 MHz Delay Locked Loop Based 128-bin, 256 ns Deep Analog Memory ASIC "Anusmriti".
Menka SukhwaniVinay Bhaskar ChandratreMegha ThomasC. K. PithawaVangmayee ShardaPublished in: ISVLSI (2011)
Keyphrases
- circuit design
- end to end delay
- memory requirements
- main memory
- integrated circuit
- design methodology
- memory usage
- application specific
- embedded dram
- high frequency
- associative memory
- memory space
- xilinx virtex
- high speed
- mixed signal
- cmos technology
- power dissipation
- wireless sensor networks
- analog circuits
- hardware architecture
- analog vlsi
- variable sized
- physical design
- higher throughput