V. K. Tomar

Publication Activity (10 Years)

Years Active: 2018-2023
Publications (10 Years): 12

Top Topics

Random Access Memory

Low Power Consumption

Top Venues

J. Circuits Syst. Comput.

Wirel. Pers. Commun.

IET Circuits Devices Syst.

Publications

Saloni Bansal, V. K. Tomar
10T SRAM cell Analysis for improved Read and Write Noise Margin. ICCCNT (2023)
V. K. Tomar, Ashish Sachdeva
Design of a soft error hardened SRAM cell with improved access time for embedded systems. Microprocess. Microsystems 90 (2022)
Harekrishna Kumar, V. K. Tomar
Design of Low Leakage 9T SRAM Cell with Improved Performance for Ultra-Low Power Devices. J. Circuits Syst. Comput. 31 (2) (2022)
Ashish Sachdeva, V. K. Tomar
Characterization of Stable 12T SRAM with Improved Critical Charge. J. Circuits Syst. Comput. 31 (2) (2022)
Harekrishna Kumar, V. K. Tomar
Design of Low Power with Expanded Noise Margin Subthreshold 12T SRAM Cell for Ultra-Low Power Devices. J. Circuits Syst. Comput. 30 (6) (2021)
Harekrishna Kumar, V. K. Tomar
A Review on Performance Evaluation of Different Low Power SRAM Cells in Nano-Scale Era. Wirel. Pers. Commun. 117 (3) (2021)
Ashish Sachdeva, V. K. Tomar
Design of Low Power Half Select Free 10T Static Random-Access Memory Cell. J. Circuits Syst. Comput. 30 (4) (2021)
Ashish Sachdeva, V. K. Tomar
A Multi-bit Error Upset Immune 12T SRAM Cell for 5G Satellite Communications. Wirel. Pers. Commun. 120 (3) (2021)
Ashish Sachdeva, V. K. Tomar
Design of 10T SRAM cell with improved read performance and expanded write margin. IET Circuits Devices Syst. 15 (1) (2021)
Deepak Mittal, V. K. Tomar
Performance Evaluation of 6T, 7T, 8T, and 9T SRAM cell Topologies at 90 nm Technology Node. ICCCNT (2020)
Ashish Sachdeva, V. K. Tomar
Design of a Stable Low Power 11-T Static Random Access Memory Cell. J. Circuits Syst. Comput. 29 (13) (2020)
Reeya Agrawal, V. K. Tomar
Analysis of Cache(SRAM) Memory for Core i™ 7 Processor. ICCCNT (2018)