Tsung-Chih Hung

Publication Activity (10 Years)

Years Active: 2016-2020
Publications (10 Years): 8

Top Topics

Weighted Averaging

Top Venues

IEEE J. Solid State Circuits

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Jia-Ching Wang, Tsung-Chih Hung, Tai-Haur Kuo
A Calibration-Free 14-b 0.7-mW 100-MS/s Pipelined-SAR ADC Using a Weighted- Averaging Correlated Level Shifting Technique. IEEE J. Solid State Circuits 55 (12) (2020)
Kuei-Yuan Wang, Ying-Li Lin, Chien-Kuo Han, Tsung-Chih Hung
Feasibility Study of Introducing Daily Rental Suites Business Model into Long-Term Care Institutions. IMIS (2020)
Tsung-Chih Hung, Jia-Ching Wang, Tai-Haur Kuo
16.4 A Calibration-Free 71.7dB SNDR 100MS/s 0.7mW Weighted-Averaging Correlated Level Shifting Pipelined SAR ADC with Speed-Enhancement Scheme. ISSCC (2020)
Tsung-Chih Hung, Tai-Haur Kuo
A 75.3-dB SNDR 24-MS/s Ring Amplifier-Based Pipelined ADC Using Averaging Correlated Level Shifting and Reference Swapping for Reducing Errors From Finite Opamp Gain and Capacitor Mismatch. IEEE J. Solid State Circuits 54 (5) (2019)
Jia-Ching Wang, Tsung-Chih Hung, Tai-Haur Kuo
A 15-bit 20 MS/s SHA-Less Pipelined ADC Achieving 73.7 dB SNDR with Averaging Correlated Level Shifting Technique. VLSI-DAT (2019)
Tsung-Chih Hung, Fan-Wei Liao, Tai-Haur Kuo
A 12-Bit Time-Interleaved 400-MS/s Pipelined ADC With Split-ADC Digital Background Calibration in 4, 000 Conversions/Channel. IEEE Trans. Circuits Syst. II Express Briefs (11) (2019)
Tsung-Chih Hung, Tai-Haur Kuo
A 40/30 MS/s Dual-Mode Pipelined ADC with Error Averaging Techniques in 90nm CMOS Achieving 71.2/74.5 dB SNDR over the Entire Nyquist Bandwidth. CICC (2019)
Tsung-Chih Hung, Tai-Haur Kuo
A 4.86 mW 15-bit 22.5 MS/s pipelined ADC with 74 dB SNDR in 90 nm CMOS using averaging correlated level shifting technique. A-SSCC (2016)