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A 40/30 MS/s Dual-Mode Pipelined ADC with Error Averaging Techniques in 90nm CMOS Achieving 71.2/74.5 dB SNDR over the Entire Nyquist Bandwidth.
Tsung-Chih Hung
Tai-Haur Kuo
Published in:
CICC (2019)
Keyphrases
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analog to digital converter
error rate
hd video
low cost
power consumption
database
cmos technology
silicon on insulator
power supply
error bounds
high speed
circuit design
sampling rate
analog vlsi
low power
single chip
bandwidth allocation
random access memory
metal oxide semiconductor
nm technology