Thomas Zeiser

Publication Activity (10 Years)

Years Active: 2003-2020
Publications (10 Years): 12

Top Topics

Lattice Boltzmann

Highly Optimized

Top Venues

Comput. Math. Appl.

Concurr. Comput. Pract. Exp.

Publications

Tirthak Patel, Adam Wagenhäuser, Christopher Eibel, Timo Hönig, Thomas Zeiser, Devesh Tiwari
What does Power Consumption Behavior of HPC Jobs Reveal? : Demystifying, Quantifying, and Predicting Power Consumption Characteristics. IPDPS (2020)
Faisal Shahzad, Jonas Thies, Moritz Kreutzer, Thomas Zeiser, Georg Hager, Gerhard Wellein
CRAFT: A Library for Easier Application-Level Checkpoint/Restart and Automatic Fault Tolerance. IEEE Trans. Parallel Distributed Syst. 30 (3) (2019)
Jan Eitzinger, Thomas Gruber, Ayesha Afzal, Thomas Zeiser, Gerhard Wellein
ClusterCockpit - A web application for job-specific performance monitoring. CLUSTER (2019)
Faisal Shahzad, Moritz Kreutzer, Thomas Zeiser, Rui Machado, Andreas Pieper, Georg Hager, Gerhard Wellein
Building and utilizing fault tolerance support tools for the GASPI applications. Int. J. High Perform. Comput. Appl. 32 (5) (2018)
Faisal Shahzad, Jonas Thies, Moritz Kreutzer, Thomas Zeiser, Georg Hager, Gerhard Wellein
CRAFT: A library for easier application-level Checkpoint/Restart and Automatic Fault Tolerance. CoRR (2017)
Markus Wittmann, Viktor Haag, Thomas Zeiser, Harald Köstler, Gerhard Wellein
Lattice Boltzmann Benchmark Kernels as a Testbed for Performance Analysis. CoRR (2017)
Nicolay Hammer, Ferdinand Jamitzky, Helmut Satzger, Momme Allalen, Alexander Block, Anupam Karmakar, Matthias Brehm, Reinhold Bader, Luigi Iapichino, Antonio Ragagnin, Vasilios Karakasis, Dieter Kranzlmüller, Arndt Bode, Herbert Huber, Martin Kühn, Rui Machado, Daniel Grünewald, Philipp V. F. Edelmann, Friedrich K. Röpke, Markus Wittmann, Thomas Zeiser, Gerhard Wellein, Gerald Mathias, Magnus Schwörer, Konstantin Lorenzen, Christoph Federrath, Ralf Klessen, Karl-Ulrich Bamberg, Hartmut Ruhl, Florian Schornbaum, Martin Bauer, Anand Nikhil, Jiaxing Qi, Harald Klimach, Hinnerk Stüben, Abhishek Deshmukh, Tobias Falkenstein, Klaus Dolag, Margarita Petkova
Extreme Scale-out SuperMUC Phase 2 - lessons learned. CoRR (2016)
Markus Wittmann, Georg Hager, Thomas Zeiser, Jan Treibig, Gerhard Wellein
Chip-level and multi-node analysis of energy-optimized lattice Boltzmann CFD simulations. Concurr. Comput. Pract. Exp. 28 (7) (2016)
Faisal Shahzad, Moritz Kreutzer, Thomas Zeiser, Rui Machado, Andreas Pieper, Georg Hager, Gerhard Wellein
Building a Fault Tolerant Application Using the GASPI Communication Layer. CLUSTER (2015)
Faisal Shahzad, Moritz Kreutzer, Thomas Zeiser, Rui Machado, Andreas Pieper, Georg Hager, Gerhard Wellein
Building a fault tolerant application using the GASPI communication layer. CoRR (2015)
Nicolay Hammer, Ferdinand Jamitzky, Helmut Satzger, Momme Allalen, Alexander Block, Anupam Karmakar, Matthias Brehm, Reinhold Bader, Luigi Iapichino, Antonio Ragagnin, Vasilios Karakasis, Dieter Kranzlmüller, Arndt Bode, Herbert Huber, Martin Kühn, Rui Machado, Daniel Grünewald, Philipp V. F. Edelmann, Friedrich K. Röpke, Markus Wittmann, Thomas Zeiser, Gerhard Wellein, Gerald Mathias, Magnus Schwörer, Konstantin Lorenzen, Christoph Federrath, Ralf Klessen, Karl-Ulrich Bamberg, Hartmut Ruhl, Florian Schornbaum, Martin Bauer, Anand Nikhil, Jiaxing Qi, Harald Klimach, Hinnerk Stüben, Abhishek Deshmukh, Tobias Falkenstein, Klaus Dolag, Margarita Petkova
Extreme Scale-out SuperMUC Phase 2 - lessons learned. PARCO (2015)
Markus Wittmann, Thomas Zeiser, Georg Hager, Gerhard Wellein
Short Note on Costs of Floating Point Operations on current x86-64 Architectures: Denormals, Overflow, Underflow, and Division by Zero. CoRR (2015)
Markus Wittmann, Thomas Zeiser, Georg Hager, Gerhard Wellein
Modeling and analyzing performance for highly optimized propagation steps of the lattice Boltzmann method on sparse lattices. CoRR (2014)
Markus Wittmann, Georg Hager, Thomas Zeiser, Gerhard Wellein
An analysis of energy-optimized lattice-Boltzmann CFD simulations from the chip to the highly parallel level CoRR (2013)
Faisal Shahzad, Markus Wittmann, Thomas Zeiser, Georg Hager, Gerhard Wellein
An Evaluation of Different I/O Techniques for Checkpoint/Restart. IPDPS Workshops (2013)
Markus Wittmann, Thomas Zeiser, Georg Hager, Gerhard Wellein
Comparison of different propagation steps for lattice Boltzmann methods. Comput. Math. Appl. 65 (6) (2013)
Markus Wittmann, Georg Hager, Thomas Zeiser, Gerhard Wellein
Asynchronous MPI for the Masses CoRR (2013)
Faisal Shahzad, Markus Wittmann, Moritz Kreutzer, Thomas Zeiser, Georg Hager, Gerhard Wellein
A Survey of Checkpoint/Restart Techniques on Distributed Memory Systems. Parallel Process. Lett. 23 (4) (2013)
Faisal Shahzad, Markus Wittmann, Thomas Zeiser, Gerhard Wellein
Asynchronous Checkpointing by Dedicated Checkpoint Threads. EuroMPI (2012)
Markus Wittmann, Thomas Zeiser, Georg Hager, Gerhard Wellein
Domain decomposition and locality optimization for large-scale lattice Boltzmann simulations CoRR (2011)
Markus Wittmann, Thomas Zeiser, Georg Hager, Gerhard Wellein
Comparison of different Propagation Steps for the Lattice Boltzmann Method CoRR (2011)
Johannes Habich, Thomas Zeiser, Georg Hager, Gerhard Wellein
Performance analysis and optimization strategies for a D3Q19 lattice Boltzmann kernel on nVIDIA GPUs using CUDA. Adv. Eng. Softw. 42 (5) (2011)
Thomas Zeiser, Georg Hager, Gerhard Wellein
Benchmark Analysis and Application Results for Lattice Boltzmann Simulations on NEC SX Vector and Intel Nehalem Systems. Parallel Process. Lett. 19 (4) (2009)
Gerhard Wellein, Georg Hager, Thomas Zeiser, Markus Wittmann, Holger Fehske
Efficient Temporal Blocking for Stencil Computations by Multicore-Aware Wavefront Parallelization. COMPSAC (1) (2009)
Thomas Zeiser, Georg Hager, Gerhard Wellein
The world's fastest CPU and SMP node: Some performance results from the NEC SX-9. IPDPS (2009)
Lilit Axner, Jörg Bernsdorf, Thomas Zeiser, Peter Lammers, Jan Linxweiler, Alfons G. Hoekstra
Performance evaluation of a parallel sparse lattice Boltzmann solver. J. Comput. Phys. 227 (10) (2008)
Georg Hager, Thomas Zeiser, Gerhard Wellein
Data access optimizations for highly threaded multi-core CPUs with multiple memory controllers. IPDPS (2008)
Georg Hager, Thomas Zeiser, Gerhard Wellein
Data Access Characteristics and Optimizations for Sun UltraSPARC T2 and T2+ Systems. Parallel Process. Lett. 18 (4) (2008)
Stefan Donath, Klaus Iglberger, Gerhard Wellein, Thomas Zeiser, Aditya Nitsure, Ulrich Rüde
Performance comparison of different parallel lattice Boltzmann implementations on multi-core multi-socket systems. Int. J. Comput. Sci. Eng. 4 (1) (2008)
Georg Hager, Holger Stengel, Thomas Zeiser, Gerhard Wellein
RZBENCH: Performance evaluation of current HPC architectures using low-level and application benchmarks CoRR (2007)
Georg Hager, Thomas Zeiser, Gerhard Wellein
Data access optimizations for highly threaded multi-core CPUs with multiple memory controllers CoRR (2007)
Thomas Pohl, Frank Deserno, Nils Thürey, Ulrich Rüde, Peter Lammers, Gerhard Wellein, Thomas Zeiser
Performance Evaluation of Parallel Large-Scale Lattice Boltzmann Applications on Three Supercomputing Architectures. SC (2004)
Jörg Bernsdorf, Uwe Jaekel, Thomas Zeiser, T. Takei, H. Matsumoto, K. Nishizawa
Lattice Boltzmann Simulation and Visualisation of Adsorption Processes in Complex Geometries. International Conference on Computational Science (2003)