Tadayoshi Horita

Publication Activity (10 Years)

Years Active: 1995-2016
Publications (10 Years): 2

Top Topics

Activation Function

Processor Array

Top Venues

Trans. Comput. Sci.

Publications

Itsuo Takanami, Tadayoshi Horita, Masakazu Akiba, Mina Terauchi, Tsuneo Kanno
A Built-in Self-repair Circuit for Restructuring Mesh-Connected Processor Arrays by Direct Spare Replacement. Trans. Comput. Sci. 27 (2016)
Tadayoshi Horita, Itsuo Takanami, Masakazu Akiba, Mina Terauchi, Tsuneo Kanno
An FPGA-Based Multiple-Weight-and-Neuron-Fault Tolerant Digital Multilayer Perceptron (Full Version). Trans. Comput. Sci. 25 (2015)
Tadayoshi Horita, Itsuo Takanami, Kazuhiro Nishimura
Multilayer Perceptrons Which Are Tolerant to Multiple Faults and Learnings to Realize Them. Trans. Comput. Sci. 22 (2014)
Tadayoshi Horita, Itsuo Takanami, Masakazu Akiba, Mina Terauchi, Tsuneo Kanno
A GPGPU-Based Acceleration of Fault-Tolerant MLP Learnings. MCSoC (2014)
Tadayoshi Horita, Itsuo Takanami
An FPGA-based multiple-weight-and-neuron-fault tolerant digital multilayer perceptron. Neurocomputing 99 (2013)
Itsuo Takanami, Tadayoshi Horita
A Built-in Circuit for Self-Repairing Mesh-Connected Processor Arrays by Direct Spare Replacement. PRDC (2012)
Tadayoshi Horita, Itsuo Takanami
An FPGA-Based Fault-Tolerant 2D Systolic Array for Matrix Multiplications. Trans. Comput. Sci. 13 (2011)
Tadayoshi Horita, Itsuo Takanami
An FPGA-based fast classifier with high generalization property. SIGARCH Comput. Archit. News 38 (4) (2010)
Tadayoshi Horita, Itsuo Takanami
An Implementation of a Fault-Tolerant 2D Systolic Array on FPGAs and Its Evaluation. PDPTA (2009)
Kazuhiro Nishimura, Tadayoshi Horita, Masato Otsu, Itsuo Takanami
Novel Value Injection Learning Methods Which Make Multilayer Neural Networks Multiple-Weight-and-Neuron-Fault Tolerant. PDPTA (2009)
Tadayoshi Horita, Koichi Kitano, Koji Teramoto
A Computer Cluster for Tests of Parallel Programming Environments Including Operating Systems. PDPTA (2009)
Tadayoshi Horita, Itsuo Takanami, Masatoshi Mori
Learning Algorithms Which Make Multilayer Neural Networks Multiple-Weight-and-Neuron-Fault Tolerant. IEICE Trans. Inf. Syst. (4) (2008)
Tadayoshi Horita, Yuuji Katou, Itsuo Takanami
An Analysis for Fault-Tolerant 3D Processor Arrays Using 1.5-Track Switches. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2008)
Tadayoshi Horita, Takurou Murata, Itsuo Takanami
A Multiple-Weight-and-Neuron-Fault Tolerant Digital Multilayer Neural Network. DFT (2006)
Tadayoshi Horita, Itsuo Takanami
Analytical Results for Reconfiguration of E-11/2- Track Switch Torus Arrays with Multiple Fault Types. PRDC (2001)
Tadayoshi Horita, Itsuo Takanami
A System for Efficiently Self-Reconstructing 1½-Track Switch Torus Arrays. PDPTA (2000)
Tadayoshi Horita, Itsuo Takanami
A System for Efficiently Self-Reconstructing E-1½-Track Switch Torus Arrays. ISPAN (2000)
Tadayoshi Horita, Itsuo Takanami
Fault-Tolerant Processor Arrays Based on the 1½-Track Switches with Flexible Spare Distributions. IEEE Trans. Computers 49 (6) (2000)
Tadayoshi Horita, Itsuo Takanami
Fault Tolerant Processor Arrays Based on 1 1/2-Track Switch with Generalized Spare Distributions. ISPAN (1999)
Itsuo Takanami, Tadayoshi Horita
A built-in self-reconfigurable scheme for 3D mesh arrays. ISPAN (1997)
Tadayoshi Horita, Itsuo Takanami
A Polynomial Time Algorithm for Reconfiguring the 1 1/2 Track-Switch Model with PE and Bus faults. ISPAN (1997)
Itsuo Takanami, Tadayoshi Horita
Self-reconstruction of mesh-arrays with 1 1/2 -track switches by digital neural circuits. DFT (1997)
Tadayoshi Horita, Itsuo Takanami
Reconfiguration of 1 1/2 track-switch mesh-arrays with PE and bus faults. DFT (1996)
Itsuo Takanami, Tadayoshi Horita
Reconfigurable architectures for mesh-arrays with PE and link faults. DFT (1995)