An FPGA-Based Fault-Tolerant 2D Systolic Array for Matrix Multiplications.

Tadayoshi Horita Itsuo Takanami

Published in: Trans. Comput. Sci. (2011)

Keyphrases

fault tolerant
systolic array
fault tolerance
reconfigurable architecture
data flow
distributed systems
parallel architecture
state machine
hardware implementation
load balancing
high availability
multimedia
multi agent
object oriented
response time
hardware architecture