Swapnil Mhaske

Publication Activity (10 Years)

Years Active: 2014-2019
Publications (10 Years): 4

Top Topics

Hardware Implementation

Mass Spectrometry Data

Top Venues

Sarnoff Symposium

Int. J. Reconfigurable Comput.

Publications

Swapnil Mhaske, Predrag Spasojevic, Ahsan Aziz
A Blockage Model for the Open Area Mm-wave Device-to-Device Environment. CoRR (2019)
Swapnil Mhaske, Hojin Kee, Tai Ly, Ahsan Aziz, Predrag Spasojevic
FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis. Int. J. Reconfigurable Comput. 2017 (2017)
Swapnil Mhaske, Predrag Spasojevic, Ahsan Aziz, Malik Muhammad Usman Gul
Link quality analysis in the presence of blockages for analog beamformed mm-wave channel. MILCOM (2016)
Swapnil Mhaske, Hojin Kee, Tai Ly, Predrag Spasojevic
FPGA-accelerated simulation of a hybrid-ARQ system using high level synthesis. Sarnoff Symposium (2016)
Swapnil Mhaske, Hojin Kee, Tai Ly, Ahsan Aziz, Predrag Spasojevic
High-Throughput FPGA-Based QC-LDPC Decoder Architecture. VTC Fall (2015)
Brennan Young, Swapnil Mhaske, Predrag Spasojevic
Rate compatible IRA codes using row splitting for 5G wireless. CISS (2015)
Swapnil Mhaske, David Uliana, Hojin Kee, Tai Ly, Ahsan Aziz, Predrag Spasojevic
A 2.48Gb/s QC-LDPC Decoder Implementation on the NI USRP-2953R. CoRR (2015)
Swapnil Mhaske, David Uliana, Hojin Kee, Tai Ly, Ahsan Aziz, Predrag Spasojevic
A 2.48Gb/s FPGA-based QC-LDPC decoder: An algorithmic compiler implementation. Sarnoff Symposium (2015)
Swapnil Mhaske, Hojin Kee, Tai Ly, Ahsan Aziz, Predrag Spasojevic
High-Throughput FPGA-based QC-LDPC Decoder Architecture. CoRR (2015)
Hojin Kee, Swapnil Mhaske, David Uliana, Adam Arnesen, Newton Petersen, Taylor L. Riché, Dustyn Blasig, Tai Ly
Rapid and high-level constraint-driven prototyping using lab VIEW FPGA. GlobalSIP (2014)