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A 2.48Gb/s FPGA-based QC-LDPC decoder: An algorithmic compiler implementation.
Swapnil Mhaske
David Uliana
Hojin Kee
Tai Ly
Ahsan Aziz
Predrag Spasojevic
Published in:
Sarnoff Symposium (2015)
Keyphrases
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highly optimized
hardware implementation
hardware architecture
ldpc codes
low density parity check
general purpose
hardware design
high speed
efficient implementation
software systems
low complexity
application specific
channel coding
java virtual machine
java bytecode