Srinivas Jallepalli

Publication Activity (10 Years)

Years Active: 1998-2016
Publications (10 Years): 2

Top Topics

Evaluation Process

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Srinivas Jallepalli, Ram Mooraka, Sanjay Parihar, Earl Hunter, Elie Maalouf
Rapid Assessment of Design Sensitivity to Process Excursions via Scaled Sigma Sampling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (6) (2016)
Srinivas Jallepalli, Ram Mooraka, Sanjay Parihar, Earl Hunter, Elie Maalouf
Employing Scaled Sigma Sampling for Efficient Estimation of Rare Event Probabilities in the Absence of Input Domain Mapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (6) (2016)
Mahbub Rashed, Wei-Kai Shih, Srinivas Jallepalli, R. Zaman, Thomas J. T. Kwan, Christine M. Maziar
A Monte Carlo study , of Electron Transport in Strained Si/SiGe Heterostructures. VLSI Design 1998 (1) (1998)
Wei-Kai Shih, Srinivas Jallepalli, C.-F. Yeap, Mahbub Rashed, Christine M. Maziar, A. F. Tasch Jr.
A Monte Carlo Study of Electron Transport in Silicon nMOSFET Inversion Layers. VLSI Design 1998 (1) (1998)
Wei-Kai Shih, Srinivas Jallepalli, Mahbub Rashed, Christine M. Maziar, A. F. Tasch Jr.
Study of Electron Velocity Overshoot in NMOS Inversion Layers. VLSI Design 1998 (1) (1998)