Sneh Saurabh

Publication Activity (10 Years)

Years Active: 2018-2024
Publications (10 Years): 21

Top Topics

Prime Implicants

Bayesian Inference

Boolean Functions

Top Venues

Publications

Pooja Beniwal, Sneh Saurabh
Artificial Neural Network-based Prediction and Alleviation of Congestion during Placement. VLSID (2024)
Pranav Jain, Gagandeep, Sneh Saurabh
FLIP: An Artificial Neural Network-based Post-routing Incremental Placer. VLSID (2024)
Shivendra Singh, Ekta Tiwari, Abhinav Gupta, Sneh Saurabh
Improving Retention Time of 1T DRAM using Electrostatic Barrier: Proposal and Analysis. VLSID (2024)
Amina Haroon, Ram Krishna Ghosh, Sneh Saurabh
Implementation of Probabilistic Bits (Pbits) using Low Barrier Magnets: Investigation and Analysis. VLSID (2023)
Syed Asrar ul Haq, Abdul Karim Gizzini, Shakti Shrey, Sumit Jagdish Darak, Sneh Saurabh, Marwa Chafii
Deep Neural Network Augmented Wireless Channel Estimation for Preamble-Based OFDM PHY on Zynq System on Chip. IEEE Trans. Very Large Scale Integr. Syst. 31 (7) (2023)
Amina Haroon, Sneh Saurabh
Image Completion using a Sparse Probabilistic Spin Logic Network. VLSID (2022)
Syed Asrar ul Haq, Abdul Karim Gizzini, Shakti Shrey, Sumit J. Darak, Sneh Saurabh, Marwa Chafii
Deep Neural Network Augmented Wireless Channel Estimation on System on Chip. CoRR (2022)
Jasmine Kaur, Sneh Saurabh, Shubham Sahay
Muller C-Element Exploiting Programmable Metallization Cell for Bayesian Inference. IEEE J. Emerg. Sel. Topics Circuits Syst. 12 (4) (2022)
Raiyyan Malik, Shubham Baunthiyal, Puneet Kumar, Srinath J, Sneh Saurabh
A Comparison of SAT-based and SMT-based Frameworks for X-value Combinational Equivalence Checking. VLSI-SoC (2022)
Akshay Balaji, Sneh Saurabh
Reducing Breakdown Voltage in a Bipolar Impact Ionization MOSFET (BI-MOS) using Gate-Source Underlap. VLSI-SoC (2021)
Mamidala Karthik Ram, Neha Tiwari, Dawit Burusie Abdi, Sneh Saurabh
Effect of Drain Induced Barrier Enhancement on Subthreshold Swing and OFF-State Current of Short Channel MOSFETs: A TCAD Study. IEEE Access 9 (2021)
O. V. S. Shashank Ram, Sneh Saurabh
Modeling Multiple-Input Switching in Timing Analysis Using Machine Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (4) (2021)
Mamidala Karthik Ram, Neha Tiwari, Dawit Burusie Abdi, Sneh Saurabh
Drain Induced Barrier Widening and Reverse Short Channel Effects in Tunneling FETs: Investigation and Analysis. IEEE Access 9 (2021)
Madhvi Agarwal, Sneh Saurabh
An Efficient Timing Model of Flip-Flops Based on Artificial Neural Network. MLCAD (2021)
Subhadip Poria, Shelly Garg, Sneh Saurabh
Suppression of Ambipolar current in Tunnel Field-Effect Transistor using Field-Plate. VDAT (2020)
Shelly Garg, Sneh Saurabh
Implementing Logic Functions Using Independently-Controlled Gate in Double-Gate Tunnel FETs: Investigation and Analysis. IEEE Access 7 (2019)
Vaibhav Agarwal, Sneh Saurabh
Application of Probabilistic Spin Logic (PSL) in Detecting Satisfiability of a Boolean Function. ISQED (2019)
Akhil James, Sneh Saurabh
Dopingless 1T DRAM: Proposal, Design, and Analysis. IEEE Access 7 (2019)
Vaibhav Agarwal, Sneh Saurabh
Realizing Boolean Functions Using Probabilistic Spin Logic (PSL). VLSI Design (2019)
Sneh Saurabh, Vishav Vikash
Assessing the Impact of Temperature and Supply Voltage Variations in Near-threshold Circuits using an Analytical Model. ACM Great Lakes Symposium on VLSI (2018)
Sneh Saurabh, Priyanka Mittal
A Practical Methodology to Compress Technology Libraries Using Recursive Polynomial Representation. VLSI Design (2018)