Sarang Kazeminia

Publication Activity (10 Years)

Years Active: 2006-2020
Publications (10 Years): 10

Top Topics

High Speed Camera

Inventory Systems

Inverted Pendulum

Top Venues

Publications

Sarang Kazeminia, Arefeh Soltani
A low-jitter leakage-free digitally calibrated phase locked loop. Comput. Electr. Eng. 88 (2020)
Sarang Kazeminia
A real-time pseudo-background gain calibration strategy for residue amplifiers of pipeline ADCs. Integr. 65 (2019)
Sarang Kazeminia, Khayrollah Hadidi
A foreground-liked continuous-time offset cancellation strategy for open-loop inter-stage amplifiers in high-resolution ADCs. Integr. 61 (2018)
Sarang Kazeminia, Maryam Ghafoorzadeh, Faeze Noruzpur
An extendable global clock high-speed binary counter compatible to the FPGA CLBs. MIXDES (2017)
Sarang Kazeminia, Arefeh Soltani
Digitally-assisted gain calibration strategy for open-loop residue amplifiers in pipeline ADCs. APCCAS (2016)
Sarang Kazeminia, Sina Mahdavi, Khayrollah Hadidi
Digitally-assisted offset cancellation technique for open loop residue amplifiers in high-resolution and high-speed ADCs. MIXDES (2016)
Sarang Kazeminia, Sina Mahdavi
A 800MS/s, 150µV input-referred offset single-stage latched comparator. MIXDES (2016)
Sarang Kazeminia, Sina Mahdavi, Reza Gholamnejad
Bulk controlled offset cancellation mechanism for single-stage latched comparator. MIXDES (2016)
Sarang Kazeminia, Arefeh Soltani
Single-stage offset-cancelled latched comparator scheduled by multi-level control on reset switch. APCCAS (2016)
Arefeh Soltani, Roozbeh Abdollahi, Sarang Kazeminia
Programmable incrementing/decrementing binary accumulator for high-speed calibration loops. ICECS (2016)
Arash Hejazi, Sarang Kazeminia, Roozbeh Abdollahi
A digitally assisted 20MHz-600MHz 16-phase DLL enhanced with dynamic gain control loop. ECCTD (2015)
Sarang Kazeminia, Khayrollah Hadidi, Abdollah Khoei
A Wide-Range Low-Jitter PLL Based on Fast-Response VCO and Simplified Straightforward Methodology of Loop Stabilization in Integer-N PLLs. J. Circuits Syst. Comput. 24 (7) (2015)
Sarang Kazeminia, Sobhan Sofi Mowloodi, Khayrollah Hadidi
A 80-MHz-to-410-MHz 16-Phases DLL Based on Improved Dead-Zone Open-Loop Phase Detector and Reduced-Gain Charge Pump. J. Circuits Syst. Comput. 24 (1) (2015)
Sarang Kazeminia, Obalit Shino, Ehsan Haghighi, Khayrollah Hadidi
Improved single-stage kickback-rejected comparator for high speed and low noise flash ADCs. ECCTD (2013)
Sarang Kazeminia, Morteza Mousazadeh, Khayrollah Hadidi, Abdollah Khoei
Single-Stage Gain-Improved and Kickback Noise Rejected Comparator in 0.35 µm 3.3 v CMOS Process. IEICE Trans. Electron. (4) (2011)
Sarang Kazeminia, Khayrollah Hadidi, Abdollah Khoei, Mohammad-Naghi Azarmanesh
Effect of bandgap energy temperature dependence on thermal coefficient of bandgap reference voltage. ECCTD (2011)
Sarang Kazeminia, Morteza Mousazadeh, Khayrollah Hadidi, Abdollah Khoei
High-speed low-power Single-Stage latched-comparator with improved gain and kickback noise rejection. APCCAS (2010)
Mohammad Soleimani, Abdollah Khoei, Khayrollah Hadidi, Sarang Kazeminia
Design of high-speed high-precision voltage-mode MAX-MIN circuits with low area and low power consumption. ECCTD (2009)
Sarang Kazeminia, Khayrollah Hadidi, Abdollah Khoei
A Novel Open Loop Structure for Phase Shifting and Frequency Synthesizing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2008)
Sarang Kazeminia, Abdollah Khoei, Khayrollah Hadidi
High Speed High Precision voltage-Mode Max and Min Circuits. J. Circuits Syst. Comput. 16 (2) (2007)
Sarang Kazeminia, Khayrollah Hadidi
An Open Loop Phase Shifter and Frequency Synthesizer. ICECS (2007)
Sarang Kazeminia, Abdollah Khoei, Khayrollah Hadidi
High Speed High Precision Voltage-Mode MAX and MIN Circuits. ICECS (2006)