Santosh Yachareni

Publication Activity (10 Years)

Years Active: 2020-2021
Publications (10 Years): 6

Top Topics

Recognition Scheme

Hardware Implementation

Top Venues

Publications

Suresh Babu Kotha, Kumar Rahul, Mohammad Anees, Santosh Yachareni, Subodh Kumar
High speed low power SEU tolerant Pseudo dual port memory in 7nm. ISNCC (2021)
Nabanita Ghoshal, Sree Rama K. C. Saraswatula, Santosh Yachareni, Shidong Zhou, Anil Kumar Kandala, Narendra Kumar Pulipati
Mitigation of the impact of across chip systematic process variation using a novel system level design. DFT (2021)
Mahendrakumar Gunasekaran, Kumar Rahul, Santosh Yachareni
Optimizing Sub bytes and Mix Column to improve performance of AES in Virtex 7 FPGA. ISNCC (2021)
Sree Rama K. C. Saraswatula, Santosh Yachareni, Shidong Zhou, Narendra Kumar Pulipati, Joy Chen, Teja Masina
Robust Adaptive Read Scheme for 7nm Configuration SRAMs. IOLTS (2021)
Kumar Rahul, Santosh Yachareni
Area and power efficient ECC for multiple adjacent bit errors in SRAMs. ICCE (2020)
Kumar Rahul, Santosh Yachareni
Deterministic Algorithm to generate SEC-DED-DAEC H-Matrix for SRAMs in FPGAs for reliable space applications. ICCCS (2020)